128Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MSDRAM_F.p65 Rev. F; Pub. 01/03

128Mb: x4, x8, x16

SDRAM

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

32 Meg x 4

16 Meg x 8

8 Meg x 16

Configuration

8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks

Refresh Count

Row Addressing

4K (A0A11)

Bank Addressing

4 (BA0, BA1)

Column Addressing

2K (A0A9, A11)

1K (A0A9)

512 (A0A8)

SYNCHRONOUS
DRAM

MT48LC32M4A2 8 Meg x 4 x 4 banks
MT48LC16M8A2 4 Meg x 8 x 4 banks
MT48LC8M16A2 2 Meg x 16 x 4 banks

For the latest data sheet, please refer to the Micron Web
site:

www.micron.com/dramds

PIN ASSIGNMENT (Top View)

54-Pin TSOP

FEATURES

· PC100-, and PC133-compliant
· Fully synchronous; all signals registered on positive

edge of system clock

· Internal pipelined operation; column address can be

changed every clock cycle

· Internal banks for hiding row access/precharge
· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge, includes CONCURRENT AUTO

PRECHARGE, and Auto Refresh Modes

· Self Refresh Mode; standard and low power
· 64ms, 4,096-cycle refresh
· LVTTL-compatible inputs and outputs
· Single +3.3V ±0.3V power supply

OPTIONS

MARKING

· Configurations

32 Meg x 4

(8 Meg x 4

x 4 banks)

32M4

16 Meg x 8

(4 Meg x 8

x 4 banks)

16M8

8 Meg x 16 (2 Meg x 16 x 4 banks)

8M16

· WRITE Recovery (

WR)

WR = "2 CLK"

· Package/Pinout

Plastic Package OCPL

54-pin TSOP II (400 mil)

60-ball FBGA (8mm x 16mm)

3,6

60-ball FBGA (11mm x 13mm)

3,6

· Timing (Cycle Time)

10ns @ CL = 2 (PC100)

-8E

3,4,5

7.5ns @ CL = 3 (PC133)

-75

7.5ns @ CL = 2 (PC133)

-7E

6.0ns @ CL=3 (x16 only)

-6A

· Self Refresh

Standard

None

Low power

· Operating Temperature Range

Commercial (0

C to +70

None

Industrial (-40

C to +85

Part Number Example:

MT48LC16M8A2TG-7E

NOTE: 1. Refer to Micron Technical Note: TN-48-05.

2. Off-center parting line.
3. Consult Micron for availability.
4. Not recommended for new designs.
5. Shown for PC100 compatability.
6. See page 59 for FBGA Device Marking Table.

DQ0

DQ1
DQ2

VssQ

DQ3
DQ4

DQ5
DQ6

VssQ

DQ7

DQML

WE#

CAS#
RAS#

CS#

BA0
BA1

A10

A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

Vss

DQ15

VssQ

DQ14
DQ13

DQ12
DQ11

VssQ

DQ10
DQ9

DQ8

Vss
NC
DQMH
CLK
CKE
NC

A11
A9
A8
A7
A6
A5
A4

Vss

x16

DQ0

DQ1

DQ2

DQ3

DQ0

NC
NC

DQ1

DQ7

DQ6

DQ5

DQ4

DQM

DQ3

NC
NC

DQ2

DQM

Note: The # symbol indicates signal is active LOW. A dash ()

indicates x8 and x4 pin function is same as x16 pin function.

KEY TIMING PARAMETERS

SPEED

CLOCK

ACCESS TIME

SETUP

HOLD

GRADE

FREQUENCY CL = 2* CL = 3*

TIME

-6A

167 MHz

5.4ns

1.5ns

0.8ns

-7E

143 MHz

5.4ns

1.5ns

0.8ns

-7E

133 MHz

5.4ns

1.5ns

0.8ns

-75

133 MHz

5.4ns

1.5ns

0.8ns

-8E

3,4,5

125 MHz

6ns

2ns

1ns

-75

100 MHz

6ns

1.5ns

0.8ns

-8E

3 ,4,5

100 MHz

6ns

2ns

1ns

*CL = CAS (READ) latency

128Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MSDRAM_F.p65 Rev. F; Pub. 01/03

128Mb: x4, x8, x16

SDRAM

FBGA BALL ASSIGNMENT

(Top View)

Depopulated Balls

Vss

VssQ

DQ3

VssQ

DQ2

Vss

DQM

CKE

A11

Vss

DQ0

VssQ

DQ1

VssQ

VDD

WE#

CAS#

RAS#

CS#

BA1

BA0

A10

32 Meg x 4

8 x 16mm and 11 x 13mm

Depopulated Balls

DQ7

Vss

VssQ

DQ6

DQ5

VssQ

DQ4

Vss

DQM

CKE

A11

Vss

DQ0

DQ1

VssQ

DQ2

DQ3

VssQ

WE#

CAS#

RAS#

CS#

BA1

BA0

A10

16 Meg x 8

8 x 16mm and 11 x 13mm

128Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MSDRAM_F.p65 Rev. F; Pub. 01/03

128Mb: x4, x8, x16

SDRAM

A0-A11 select the row). The address bits registered
coincident with the READ or WRITE command are used
to select the starting column location for the burst
access.

The SDRAM provides for programmable READ

or WRITE burst lengths of 1, 2, 4, or 8 locations, or the
full page, with a burst terminate option. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst sequence.

The 128Mb SDRAM uses an internal pipelined

architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while access-
ing one of the other three banks will hide the precharge
cycles and provide seamless high-speed, random-access
operation.

The 128Mb SDRAM is designed to operate in 3.3V

memory systems. An auto refresh mode is provided, along
with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operat-

ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between in-
ternal banks in order to hide precharge time and the
capability to randomly change column addresses on each
clock cycle during a burst access.

GENERAL DESCRIPTION

The Micron

128Mb SDRAM is a high-speed CMOS,

dynamic random-access memory containing 134,217,728
bits. It is internally configured as a quad-bank DRAM
with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the x4's
33,554,432-bit banks is organized as 4,096 rows by 2,048
columns by 4 bits. Each of the x8's 33,554,432-bit banks is
organized as 4,096 rows by 1,024 columns by 8 bits. Each
of the x16's 33,554,432-bit banks is organized as 4,096
rows by 512 columns by 16 bits.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coinci-
dent with the ACTIVE command are used to select the
bank and row to be accessed (BA0, BA1 select the bank;

PART NUMBER

ARCHITECTURE

MT48LC32M4A2TG

32 Meg x 4

MT48LC32M4A2FC*

32 Meg x 4

MT48LC32M4A2FB*

32 Meg x 4

MT48LC16M8A2TG

16 Meg x 8

MT48LC16M8A2FC*

16 Meg x 8

MT48LC16M8A2FB*

16 Meg x 8

MT48LC8M16A2TG

8 Meg x 16

*See page 59 for FBGA Device Marking Table.

128Mb SDRAM PART NUMBERS

128Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MSDRAM_F.p65 Rev. F; Pub. 01/03

128Mb: x4, x8, x16

SDRAM

TABLE OF CONTENTS

Functional Block Diagram 32 Meg x 4 .................

Functional Block Diagram 16 Meg x 8 .................

Functional Block Diagram 8 Meg x 16 .................

Pin Descriptions ........................................................

Functional Description ...........................................

Initialization .........................................................

mode register ..................................................

Burst Length ..............................................

Burst Type .................................................. 10
CAS Latency .............................................. 11
Operating Mode ........................................ 11
Write Burst Mode ...................................... 11

Commands ................................................................ 12

Truth Table 1 (Commands and DQM Operation)

............. 12

Command Inhibit ................................................ 13
No Operation (NOP) ............................................ 13
Load mode register .............................................. 13
Active .................................................................... 13
Read .................................................................... 13
Write .................................................................... 13
Precharge .............................................................. 13
Auto Precharge ..................................................... 13
Burst Terminate ................................................... 13
Auto Refresh ......................................................... 14
Self Refresh ........................................................... 14

Operation ................................................................... 15

Bank/Row Activation ........................................... 15
Reads .................................................................... 16
Writes .................................................................... 22
Precharge .............................................................. 24
Power-Down ......................................................... 24
Clock Suspend ...................................................... 25
Burst Read/Single Write ...................................... 25

Concurrent Auto Precharge ................................ 26

Truth Table 2 (CKE)

................................................... 28

Truth Table 3 (Current State, Same Bank)

...................... 29

Truth Table 4 (Current State, Different Bank)

.................. 31

Absolute Maximum Ratings ..................................... 33
DC Electrical Characteristics

and Operating Conditions ..................................... 33

Specifications and Conditions ........................... 33

Capacitance ............................................................... 34

AC Electrical Characteristics and Recommended

Operating Conditions (Timing Table) .............. 34

Timing Waveforms

Initialize and Load mode register ....................... 37
Power-Down Mode .............................................. 38
Clock Suspend Mode ........................................... 39
Auto Refresh Mode .............................................. 40
Self Refresh Mode ................................................ 41
Reads

Read Without Auto Precharge .................... 42
Read With Auto Precharge .......................... 43
Single Read Without Auto Precharge ......... 44
Single Read With Auto Precharge .............. 45
Alternating Bank Read Accesses .................... 46
Read Full-Page Burst .................................... 47
Read DQM Operation .................................. 48

Writes

Write Without Auto Precharge .................. 49
Write With Auto Precharge ........................ 50
Single Write Without Auto Precharge ....... 51
Single Write With Auto Precharge ............. 52
Alternating Bank Write Accesses ................... 53
Write Full-Page Burst ................................... 54
Write DQM Operation ................................ 55

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